The present invention relates to an interposer and more particularly to an interposer (it is also referred to as an interposer board) that is interposed between a wiring board and an electronic element (for instance, a semiconductor chip) mounted on the wiring board and used to form a semiconductor device or other electronic devices. The present invention also relates to a method for producing such an interposer and a semiconductor device or other electronic devices in which the interposer is incorporated.
As well known, the semiconductor device is formed by mounting a semiconductor chip such as an IC chip or an LSI chip on a wiring board, for instance, a multi-layer circuit board. Further, to meet the miniaturization of the semiconductor device, the interposer is frequently interposed between the wiring board and the semiconductor chip. For instance, Patent Document 1 discloses a semiconductor device in which a semiconductor chip is faced down and connected to an interposer by a solder bump and a gap between the surface of the semiconductor chip and the interposer is filled with an under-fill material. The interposer has a through electrode passing through its inner part, a wiring electrode at a position corresponding to the electrode of the semiconductor chip on one surface and an external connecting terminal (an electrode pad) for connecting the wiring board to the semiconductor chip on the other surface.
Usually, in the interposer, an epoxy resin substrate is ordinarily used as its substrate, through holes are opened on the substrate, and then, the through holes are respectively filled with an electric conductive paste, or through electrodes are formed by an electrolytic plating process. However, recently, to miniaturize the semiconductor device, reduce the thickness of the semiconductor device and improve a performance thereof, a high density mounting has been demanded. For satisfying this demand, a hard and heat resistant silicon substrate has been used in place of the epoxy resin substrate. Since the silicon substrate can especially reduce its thickness and is hard, reliability during mounting or bonding the semiconductor chip can be improved. Further, since the silicon substrate is heat resistant, even when the silicon substrate is exposed to high temperature during a producing process of the semiconductor device, a warp or a deformation does not arise.
In producing the interposer made of the silicon substrate, the through holes are ordinarily formed by using a reactive ion etching method (RIE) or a laser drilling method. Further, since the through electrode or wiring can be finely processed, the use of a damascene system or a WLP (Wafer Level Package) system is proposed. In the damascene system, for instance, after a seed layer is formed in a previously formed through hole by a CVD method (a chemical gas phase growth method) or a sputtering method, the through hole is filled with copper by an electrolytic plating process. Finally, excessive copper on a surface is removed by a chemical and mechanical polishing method (CMP) (for instance, see Non-Patent Document 1). Further, in the WLP system, for instance, processes of forming a seed layer, patterning a resist, an electrolytic plating, separating the resist and removing the seed layer are sequentially carried out. However, when these systems are carried out, the processes are undesirably long and complicated and a production cost is inconveniently increased. Further, especially, since a CMP polishing machine, a CVD device and a sputtering device need to be employed, a problem arises that the cost of devices is high. Further, since the processes are complicated, a problem arises that a package is hardly miniaturized due to a multi-layer structure. [Patent Document 1] JP-A-2000-31345 (claims, FIG. 1) [Non-Patent Document 1] K. Takahashi et al., Process Integration of 3D Chip Stack with Vertical Interconnection, p. 601-609, 2004 Electronic Components and Technology Conference